VLSI Design Projects sits within Projects at KAUSTYA. Each page below covers one capability in detail — what it involves, where it is used and how a project or programme is run.
Everything in this section
- RTL Design
- Verilog HDL Design
- VHDL Design
- Front-End Design
- Back-End Physical Design
- Design Verification
- Functional Verification
- UVM Verification
- Design for Testability (DFT)
- Static Timing Analysis
- Floorplanning, Placement and Routing
- ASIC Design
- FPGA Design and Prototyping
- SoC Design
- Analog and Mixed Signal Design
- Low Power Design
Next step
Open the page closest to your requirement, or send us a note and we will recommend the right starting point.